NANOSIL - silicon-based nanostructures and nanodevice for long term nanoelectronics applications

Supervisor :
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Prof. Romuald B. Beck, Ph.D., D.Sc.
+48 22 234 52 38
+48 22 234 75 34

Project coordinator: INPG Enterprise S.A. France.

Partners: Institut National Polytechnique de Grenoble, France; The University of Warwick, United Kingdom; Rheinisch-West­faelische Technische Hochschule Aachen, Germany; Kungliga Tekniska Hogskolan, Sweden; Consiglio Nazionale Interunuiversi­tario per la Nanoelettronica, Italy; Universite Catholique de Lou­vain, Belgium; Interuniversitair Micro-Electronica Centrum VZW, Belgium; Commisariat a L`Energie Atomiue, France; Stmicroelec­tronics Crolles 2 SAS, France; Institut Superieur D`Electronique et du Numerique, France; Universite Paris-Sud, France; Gesellschaft Fuer Angewandte Mikro- und Optoelektronik mit Beschrankter Haftung — AMO GmbH, Germany; Forschungszentrum Juelich GmbH, Germany; Qimonda Dresden GmbH & Co.OHG, Ger­many; Technische Universitaet Braunschweig, Germany; Univer­sitaet Stuttgart, Germany; National Centre for Scientific Research Demokritos, Greece, University College Cork — national Univer­sity of Ireland, Cork, Ireland; Universidad Rovira i Virgili, Spain; Chalmers Tekniska Hoegskola Aktiebolag, Sweden; Ecole Poly­technique Federale de Lausanne, Switzerland; Eidgenoessische Technische Hochschule Zuerich, Switzerland; Synopsys Switzer­land LLC, Switzerland; The University og Glasgow, United King­dom, University of Liverpool, United Kingdom; The University ogf Newcastle Upon Tyne, United Kingdom.

Aim of project: Realization of research for the semiconductor in­dustry targeted at n+4 generation of CMOS integrated circuits and new concepts of device construction and their technolo­gy. The consortium members exhibit complementary skills and competences in the field of modeling, technology and diagnos­tics and characterization of semiconductor devices and inte­grated circuits. During the project realization it is planned, among others, to test new gate structure and device channel materials (both non-strained and strained), Schottky barriers as carrier emitters. New mathematical-physical models will also be developed of complete devices electrical behavior and of their functional parts, as well as of the evaluation of their electro-physical prop­erties from test structures characteristics. Adaptation of classical characterization methods and devel­opment of novel ones, especially — of electrical characterization methods — is also planned.

Expected results: The obtained knowledge, skills and, above all, results will be transferred to IC manufacturers as a starting point in their individual studies aiming at introduction of new genera­tions of integrated circuits into production.